GATE & PSUs - Computer Science & Information Technology (CS & IT)

Cache Memory Mapping & Miss Penalties question bank (Computer Organization & Architecture (COA))

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Q1.

[Cache Memory Mapping & Miss Penalties Concept 2] A 5-stage instruction pipeline has stage delays of 150 ps, 120 ps, 160 ps, 140 ps, and 110 ps. The pipeline register delay is 10 ps. What is the clock cycle time and ideal maximum speedup compared to an unpipelined processor?

(A)

Clock period = 170 ps; Ideal speedup $\approx 4.0$ times

(B)

Clock period = 160 ps; Ideal speedup $\approx 5.0$ times

(C)

Clock period = 680 ps; Ideal speedup $\approx 1.0$ times

(D)

Clock period = 150 ps; Ideal speedup $\approx 4.5$ times

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Q2.

[Cache Memory Mapping & Miss Penalties Concept 7] A 5-stage instruction pipeline has stage delays of 150 ps, 120 ps, 160 ps, 140 ps, and 110 ps. The pipeline register delay is 10 ps. What is the clock cycle time and ideal maximum speedup compared to an unpipelined processor?

(A)

Clock period = 170 ps; Ideal speedup $\approx 4.0$ times

(B)

Clock period = 160 ps; Ideal speedup $\approx 5.0$ times

(C)

Clock period = 680 ps; Ideal speedup $\approx 1.0$ times

(D)

Clock period = 150 ps; Ideal speedup $\approx 4.5$ times

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